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Numerical Analysis of Self-Heating in Silicon Devices

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dc.contributor.author Malik, Faraz Kaiser
dc.date.accessioned 2023-08-01T07:01:16Z
dc.date.available 2023-08-01T07:01:16Z
dc.date.issued 2020
dc.identifier.other 00000276894
dc.identifier.uri http://10.250.8.41:8080/xmlui/handle/123456789/35358
dc.description Supervisor: Dr. Tariq Talha en_US
dc.description.abstract The electronics industry has pursued the aggressive miniaturization of solid-state devices to meet future technological demands, which has resulted in a significant increase in the chip transistor count and power density as device dimensions have been downscaled into the nanoscale regime. Nanoscale materials exhibit notably different characteristics from their bulk counterparts due to quantum confinement effects and changes in the mechanism of transport of the energy carriers at shorter length scales. The resistive heating of electronic devices during their operation is the single biggest hindrance to the efficient, safe, and reliable operation of these devices, since the thermal and electrical conductivities of most materials are adversely affected by a reduction in spatial dimensions and an increase in lattice temperatures, which creates a positive feedback loop that can lead to thermal runaway and breakdown as device dimensions are reduced. The study of the electrical and thermal properties of ultra-short nanoscale devices that operate in the ballistic transport regime, and the variation of these properties with device geometry and operating conditions, is therefore necessary to allow for the development of thermally-aware device designs and cooling methods in the future. This work uses the numerical Monte Carlo approach to simulate the carrier transport through nanoscale bulk silicon and one-dimensional silicon devices that serve as simplified models of nanoscale transistors. The simulations are performed over a range of operating conditions (applied voltage and initial temperature) and for different geometric specifications (channel length, electrode length, electrode doping) that are likely to be encountered in future device applications. The impact of changes in the carrier transport mechanism that are brought about by a reduction in the dimensions of characteristic device features on the device performance and the generation of localized thermal hotspots is thereby investigated systematically en_US
dc.language.iso en en_US
dc.publisher College of Electrical & Mechanical Engineering (CEME), NUST en_US
dc.subject Key Words: Joule Heating, Nanoscale Devices, Nanoscale Silicon, Monte Carlo Method, Solid-state Electronics en_US
dc.title Numerical Analysis of Self-Heating in Silicon Devices en_US
dc.type Thesis en_US


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