Development of Verification IP (VIP) for RISC-V based Microprocessors

Abstract

RISC-V is an open source modular ISA and is becoming a popular choice for building custom solutions. As the core’s usage in SoCs and micro-controllers grows, engineering teams face new verification challenges related both to the RISC-V core itself and the system based around it. Clearly, the challenge scales with multiple cores parameters, the addition of off-the-shelf peripherals and custom hardware modules. The aim of this project is to develop a scale-able UVM-based verification IP (VIP) for RISC-V based SoC processors. The approach I used for this project is that we have developed block level VIPs for all the Peripheral blocks and some of the internal blocks like ALU and Decoder. In the final step, we have integrated all the verification environment all together to develop a system level VIP for RISC-V Based Core.