Abstract:
RF front-end of modern phased array radars are composed of TR modules which differentiate them
from conventional mechanical radar. TR modules include specially designed MMIC mainly including
phase shifters, attenuator, low noise amplifier, high power amplifier and TR switches. The objective of
thesis is to develop a high-performance core chip (composed of phase shifter and attenuator) specially
tailored for AESA radar. It highlights the key requirements of AESA radar system architectures type
and functionality keeping the confinement in size and challenges. Special emphasis is given to factors
such as power handling, linearity, frequency agility, rms phase error, rms amplitude error, noise figure
and gain. Based on analysis, Common leg topology circuit is proposed for designing and integrating of
MMIC. The design process involves key components such as single pole double throw switch, 6-bit
digital phase shifter, 6-bit digital step attenuator, voltage gain amplifiers, and state switch circuit.
Computer simulations are carried out on Keysight ADS software using Wolfspeed GaN 0.15um PDK
including block diagram circuit and momentum layout circuit. All results have been carried out by
optimization on individual circuit level. For achieving realistic results and computing errors among
them, monte-carlo simulations are also performed to ensure the reliability of the core chip MMIC.
The outcome of this thesis is a high-performance core chip specifically for AESA radar system. The
proposed architecture and design promote the advanced capabilities of AESA radar enabling enhanced
detection, tracking, surveillance, and image functionalities. The findings of this this would bring
practical implications for the development of indigenous advanced radar system in military, aerospace,
and surveillance applications.
