Securing the Secure: Securing AES Implementation Against SIFA and SCA Attacks

Abstract

The rapid advancements in digitization with wide adoption of 5G/6G and IoT highlights the importance of edge devices likes smart cards that connect us to the internet. These edge devices provides us numerous benefits but also poses significant threat if side channel analysis (SCA) and Fault Injects (FI) are exploited. Despite existing countermeasure the attacks are evolving With Statistical Ineffective Fault Attacks (SIFA) being the latest attack posing real threads to cryptograhic devices. SIFA is especial in way that induction of such faults doesn’t alters the output, thus making it difficult to detect fault, which is the core requirement for fault countermeasures. This thesis presents the RTL implementation of AES hardware accelerator based on Toffoli gate as basic building circuit. Reversible logic circuit like toffoli gate have been show in literature to propagate faults even ineffective faults induced by SIFA. Masked implementation of the whole design with spatial redundancy, to detect faults, has been used to provide a combined countermeasure against the SIFA and SCA.