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Accelerating the IP Verification Coverage Closure through Machine Learning Within the UVM Framework

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dc.contributor.author Shah, Syed Jawad Hussain
dc.date.accessioned 2024-09-26T09:33:03Z
dc.date.available 2024-09-26T09:33:03Z
dc.date.issued 2024
dc.identifier.other 400508
dc.identifier.uri http://10.250.8.41:8080/xmlui/handle/123456789/46895
dc.description Supervisor: Dr. Muhammad Imran; Co-Supervisor:Dr. Haroon Waris en_US
dc.description.abstract This proposal outlines the utilization of AI and ML algorithms within the UVM framework to enhance the stimulus selection process in design verification. With the exponential growth in system complexity, efficient verification methodologies are essential. The proposed approach addresses this challenge by employing AI techniques, such as K-means clustering, to identify the most effective stimuli from a set of multiple stimuli for a specific design within the UVM framework. By analyzing the design’s characteristics and the stimuli’s impact, the AI system will intelligently select and generate stimuli, thereby improving verification efficiency. The study focuses on developing AI models tailored for this task and evaluating their effectiveness in reducing verification time and resources while ensuring comprehensive coverage. By implementing the AI and ML model, we observed a 49% improvement in transactions and a significant reduction in the time required to achieve 100% functional coverage. en_US
dc.language.iso en en_US
dc.publisher School of Electrical Engineering and Computer Science,(SEECS) NUST Islamabad en_US
dc.title Accelerating the IP Verification Coverage Closure through Machine Learning Within the UVM Framework en_US
dc.type Thesis en_US


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