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High-Throughput Impedance-Measurement IC using Periodic Integration Technique

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dc.contributor.author Ellahi, Karam
dc.date.accessioned 2024-12-27T05:18:41Z
dc.date.available 2024-12-27T05:18:41Z
dc.date.issued 2024
dc.identifier.other 364205
dc.identifier.uri http://10.250.8.41:8080/xmlui/handle/123456789/48607
dc.description Supervisor: Dr. Hammad M. Cheema en_US
dc.description.abstract Electrical impedance tomography (EIT) is a non-invasive and radiation-free imaging technique used to create impedance images of a target area. It has been successfully applied in various biomedical applications, including lung ventilation monitoring, cardiac activity assessment, breast cancer detection, and cerebral blood flow monitoring. These applications demand highly accurate and efficient impedance measurement systems capable of real-time data acquisition while maintaining low power consumption. This thesis presents the design and implementation of a high-throughput impedance readout integrated circuit (IC) that utilizes a novel synchronous cyclic integration technique with a scalable capacitive transimpedance stage. The proposed readout architecture eliminates the need for a traditional low-pass filter (LPF) in the signal chain, which typically adds complexity and power overhead. By integrating the I/Q demodulation within a single cycle, this approach significantly enhances measurement speed and accuracy while reducing the system's latency and power consumption. The results demonstrate that the proposed IC provides a promising solution for next-generation impedance measurement systems, offering a combination of high accuracy, low power consumption, and high throughput. One of the key features of this design is its ability to achieve a throughput of 50 kilo samples per second (kSps) at the highest operating frequency of 100 kHz, making it suitable for real-time applications where high-speed impedance measurements are essential. The scalable capacitive transimpedance stage also allows the architecture to be adapted for different impedance ranges, providing flexibility for various applications. The proposed IC is fabricated using a 180-nm CMOS process and consumes 50 μW from a 1.2-V supply. This makes it ideal for low-power applications, including portable medical devices, wireless sensor nodes, and other energy-sensitive applications. The IC supports impedance measurements over a wide frequency range, from 100 Hz to 100 kHz, achieving a high measurement accuracy of 99.7%. en_US
dc.language.iso en en_US
dc.publisher School of Electrical Engineering and Computer Sciences (SEECS), NUST en_US
dc.subject Electrical impedance tomography, Bioimpedance, Synchronous cyclic integration, High throughput, I/Q demodulation en_US
dc.title High-Throughput Impedance-Measurement IC using Periodic Integration Technique en_US
dc.type Thesis en_US


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