Synthesizable Digital LDO with Adaptive Gain Control Suitable for Microprocessor SoCs

Abstract

Power management is a critical aspect of modern microprocessor-based systems-on-chips (SoCs), which are at the heart of applications like mobile devices, embedded systems, and high-performance computing platforms. As these devices become increasingly complex, efficient power delivery becomes essential for optimizing performance, extending battery life, and ensuring system reliability. Voltage regulators, particularly Low Dropout (LDO) regulators, play a key role in achieving these goals. However, designing LDOs that can effectively manage dynamic load conditions, maintain high regulation accuracy, and minimize power loss presents significant challenges. This thesis introduces an innovative fully integrated digital Low Dropout Regulator (DLDO) that addresses these challenges by leveraging advanced techniques such as a multi-bit shift handler (MBSH), a decremental gain PMOS array, and an adaptive coarse loop controller. These features enable the DLDO to provide rapid load transient responses, superior line and load regulation, and improved overall power efficiency. A primary problem in power management systems is reducing voltage undershoot during load current transients, which may result in instability or poor performance. An undershoot limiter loop (ULL) is being proposed that significantly mitigates the voltage undershoot, hence providing stable operation during abrupt load variations. The proposed DLDO includes a synchronized fine-loop freezer (FLF) in its fine-loop. This method activates only when the regulator voltage (VREG) matches the reference voltage (VREF), hence reducing quiescent current (IQ) and steady-state voltage ripples (VRIPP) to enhance the regulator's overall efficiency and stability. The proposed DLDO was designed and fabricated using a 180-nm CMOS technology, occupying a tiny active area of 0.22 mm². The simulation results confirm the effectiveness of the design, showing a low voltage ripple (VRIPP) of ≤130 μV, a minimal dropout voltage of just 20 mV, apeak current efficiency of 99.96% and power efficiency of 97.49%. The results demonstrate excellent performance of the proposed DLDO, making it an ideal component for integration into modern SoCs.