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Fast Transient Dual Mode Low Dropout Regulator for Power Management in SoCs

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dc.contributor.author Qaisar, Shirin
dc.date.accessioned 2024-12-27T05:53:54Z
dc.date.available 2024-12-27T05:53:54Z
dc.date.issued 2024
dc.identifier.other 361368
dc.identifier.uri http://10.250.8.41:8080/xmlui/handle/123456789/48610
dc.description Supervisor: Dr. Hammad M. Cheema en_US
dc.description.abstract This work presents an Analog-assisted Fast-transient Digital Low Dropout (LDO) regulator for power management systems through an innovative integration of Analog and Digital control loop methodologies. The design contains a charge-pump-based fine loop to provide accurate voltage regulation, attaining an output voltage ripple of merely 0.14 mV. The Digital LDO, on the other hand, indicates steady-state voltage ripples (VRIPP) below 140 μV and functions with a minimum dropout voltage of 20 mV, making it suitable for both noise-sensitive analog circuits and power-efficient digital regulators in system-on-chip (SoC) devices. A key feature of this architecture is the steady-state control system making use of a voltage-to interval converter and a charge pump. This method successfully eliminates VRIPP, giving improved stability in steady-state conditions. The rapid transient response of the regulator is achieved by combining dual-edge-triggered shift registers (DTSR) in the coarse loop, facilitating quick adjustments to abrupt variations in load current (ILOAD). Additionally, the design adds an Analog-assisted (AA) loop, which is necessary for reducing voltage undershoots during load variations, hence providing definitive performance in dynamic settings. Digital LDO regulator is designed in 180-nm CMOS technology, occupying an active area of 0.253 mm². Simulated results demonstrate a line regulation of 8 mV/V and a load regulation of 0.081 mV/mA. This LDO regulator is capable to deliver a maximum load current of 75 mA with a peak current efficiency of 99.93%, rendering it an efficient and feasible option for modern power management needs. This architecture attains rapid transient response and minimum voltage ripples, creating a new standard in voltage regulation. Its distinctive properties make it suitable for complex applications in portable electronics, high-speed processors, and other systems needing stable, efficient, and noise-free power supply. It enhances ripple suppression and transient performance, making itself a state-of-the-art solution for next-generation power management in SoC devices. en_US
dc.description.sponsorship Sponsored by Dr. Sohmyung Ha and Dr. Abrar Akram. en_US
dc.language.iso en en_US
dc.publisher School of Electrical Engineering and Computer Sciences (SEECS), NUST en_US
dc.subject Low Dropout Regulator (LDO), Digital LDO (DLDO), Analog LDO (ALDO), Hybrid LDO (HLDO), Dual-Edge-Triggered Shift Registers (DTSR), Analog Assisted (AA) Loop en_US
dc.title Fast Transient Dual Mode Low Dropout Regulator for Power Management in SoCs en_US
dc.type Thesis en_US


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