Abstract:
In today‟s wireless communication systems one of the most important parts of transceiver system is the Power amplifier. A good power amplifier is one which can maintain its linearity and provide good efficiency over the change of input power. Different techniques have been used to achieve linearity and efficiency whilst keeping the size of amplifier as low as possible.
In this thesis the design consideration of such a power amplifier is considered for the frequency of WIFI and Bluetooth to provide output power of 16 dB for single stage with 40% Power added efficiency (PAE) and 30 dB for two-stage power amplifier. The techniques which are used to achieve the desired objectives are optimum impedance matching and harmonic suppressions circuits using both the transmission lines and lumped components. Here the harmonic suppression circuit helps to ground the harmonics which overall enhances the efficiency of Power amplifier up to 7% and provides linearity over the gain.
Simulation results show that the power amplifier delivers 17.5 dB gain for single stage with 52% maximum Power added efficiency and 36 dB gain for two-stage power amplifier. The value of Stability factor should be above 1 in order to prevent the amplifier from oscillating. In this Power amplifier the stability factor was measured to be 1.17 and it remains above 1 for the whole bandwidth of WIFI and Bluetooth.
The CMOS design of the proposed Power Amplifier is also presented. The CMOS IC consists of 5 pins where Pin 1 and 2 are RF input and output respectively, Pin 3 is VCC whereas Pin 4 and 5 are Ground pins. Two coupling capacitors C1 and C2 are connected at the input and output ports and a resistor R1 is placed at the VCC pin.
The measured results show that the Power amplifier delivers output gain of 16.7 dB in case of single stage amplifier and 30.5 dB in case of two stage Power amplifier.
