A Novel Architecture for High Quality AWGN Generation Based on Central Limit Theorem

Abstract

Gaussian Random Numbers (GRNs) are required for simulations in a wide variety of applications. For example, channel code evaluation, simulation of economic systems and product failure simulations, etc. Mostly, simulations are carried out using systems based on digital signal processor or other software programmable devices. Such systems generate GRNs using software libraries to evaluate complex trigonometric functions like natural logarithm, exponential functions, etc. However, optimized hardware implementation of GRNs generator can operate many times faster than optimized software implementations. Hardware implementation of GRNs generator generally involves transformation of uniformly distributed random numbers and has always been a challenging task. Central Limit Theorem (CLT), although very simple to implement, has never been used to generate high quality GRNs. This is because the direct implementation of CLT provides very poor accuracy in the tail region of probability density function (PDF). This work achieves high quality GRNs generator. The empirical model of the error in CLT is compensated through deployment of a low complexity compensation block. A novel non-uniform segmentation algorithm is presented for degree one piecewise polynomial approximation to non-linear error function. We have proposed a novel architecture of GRNs generator which requires only 420 configurable slices and 01 DSP block of Xilinx Virtex-4 XC4VLX15 operating at 220 MHz. The architecture achieves high tail accuracy of 6 and is scalable to achieve even higher accuracy with minimal increase in hardware resources. The accuracy of GRNs generator is validated using statistical goodness of fit tests.