Hardware Based Platform Independent Rendering for Multi-Projector Display

Abstract

Multi-projector walls are being widely used for the construction of large panoramic views, due to their ability to deliver great visual experience in a cost-efficient manner. To generate seamless projection on such surfaces two major corrections are required: geometrical correction and the photometric correction. Geometric correction is performed to align the projected contents across multiple projectors and also to account for the distortions that appear due to the surface shape. Photo-metric corrections are performed to make the projection seamless across the projector boundaries. When the surface is planar, homography defines the relation to align the projected contents using 8 transformation parameters. However when the surface is curved further higher order warping is required and that complexity of such transformations is based on the complexity of surface. A geometric correction comprising homography and second order Bezier transformation can be employed to perform multi-projector projection on quadratic surfaces. Most of the existing correction systems are implemented in software, where correction program interrupts the video stream going to graphics chip, applies correction and finally sends out to the DVI/VGA port. For the software based solutions, GPUs are widely used for their capability to handle multiple threads at a time. Such software based solutions also share some resources with the system and hence affect the system performance. Some hardware based solutions were also developed, but they are mainly existed for low resolution images. In this work, feasibility study is performed, and architecture is proposed for performing homography and Bezier transform in real time. This architecture can easily be implemented on FPGAs and can be fabricated into ASICs. The proposed system can be installed at any Video output channel; hence it removed the platform dependency. Second order Bezier transform is used to apply geometric correction to the video stream. After the successful simulations, the xi design was tested on Xilinx Spartan 3A (DSP Video Starter Kit). The system was tested for resolutions up to 1024*768 with the frame rate of 75fps, but the current implementation can easily handle incoming video having resolutions up to 1600*1200. Also, the system was tested using DVI input and output ports, which can be easily changed for HDMI or other video standards.