Hardware Architecture of Reconfigurable Multiple Input Multiple Output (MIMO) Channel Emulator

Abstract

Multiple Input Multiple Output (MIMO) wireless channel models require huge computational power and cannot be executed in real-time even on the state of art computers. In this work, we present scalable hardware architecture of a MIMO channel emulator that can support a data rate of up to 150-Mbps in real-time. Designed emulator uses a single FPGA for real-time emulation of 4×4 MIMO configuration and can be easily scaled up for higher configurations with additional hardware. The emulator comprises one of the most popular and statistically accurate MIMO wireless channel model entitled as “Kronecker Model”. The architecture has been implemented on a single Xilinx FPGA operating at 73 MHz utilizing 9% memory, 83 % logic and 100% DSP slices. The DSP slices‟ utilization is 100 % due to Xilinx‟s own logic mapping, the actual consumption is far less than 100 %. Statistical accuracy of the emulator has been verified both in time and frequency domains. Hardware efficiency (area, power and speed), of the designed emulator is better than all the previously reported emulators which are surveyed in detail. The architecture can be easily extended to support higher number of channels and data rate.