POWER EFFICIENT MICRO-CODED INSTRUCTION BASED ARCHITECTURE FOR EXPRESS STANDARDS EXTENDED TO USB 3.0

Abstract

Emerging high speed communication protocols with ultra high bandwidth requirement demand efficient system architecture design to meet their specifications. Universal Serial Bus (USB) 3.0 supporting 4.8 Gbps, PCI express providing 5Gbps and Intel’s forthcoming light peak supporting 10Gbps are some of the examples. Both streaming and non-streaming high-end digital devices such as HD cameras, webcams and mass storage devices employing these communication standards demand efficient system architecture that provides the required bandwidth with as little processing overhead (interrupts) for CPU as possible. Also with the substantial enhancement in digital systems, there is a demand of system architecture that consumes lesser power. The importance of low power consumption is due to the ever decreasing feature size of microelectronic circuits, higher clock frequencies and larger die sizes; also because of the growing number of mobile and battery-operated systems. So, the key requirement is to minimize the interrupts, improve power consumption, reduce possible high clock speed requirements for embedded host controller, provide flexibility and all processing should be done through the centralized location. Firstly, this thesis presents novel micro-coded instruction-based system architecture of USB 3.0. The micro-coded based design implicitly performs all DMA operations with minimum hardware resources and interrupts; consequently decreasing the architectural complexity, cost, area deployment and dynamic power consumption. Secondly, we propose clock gating in our novel micro-coded system architecture that decreases the dynamic power dissipation by stopping the clock switching activity of the unused functional blocks of the whole architecture. We have applied clock gating technique both on ASIC as well as on FPGA based technology. Experiments shows that by apply clock gating dynamic power consumption decreases up to 12% iii with slight area overhead of 2% in ASIC technology; whereas in FPGA dynamic power reduced up to 15% with an 3% increase in area deployment. Furthermore, the designed system architecture increases flexibility as it will be easily extendible to forthcoming standards like PCI express and fiber optic